A DRAM having a stack-type or trench-type memory capacitor and a MOS transistor for switching is mainly used as a semiconductor memory device with a high density. However, further miniaturization of the memory capacitor is difficult, and therefore miniaturization of the DRAM is also going to show a limitation. Under such a circumstance, a semiconductor memory device is being developed, which is of a type constituting a memory cell by only one memory transistor by concurrently using a switching transistor as a capacitor element instead of using the aforementioned stack-type or trench-type memory capacitor. For example, Non-Patent Document 1 as described below discloses a semiconductor memory device in which electric charges are accumulated in a floating body region of an SOI transistor.
Non-Patent Document 1: DIGEST OF TECHNICAL PAPERS pp 152-153, “9.1 Memory Design Using One-Transistor Gain Cell on SOI”, Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asano, Kazumasa Sunouchi, 2002 IEEE International Solid-State Circuits Conference, Feb. 5, 2002.
Also, similarly to Non-Patent Document 1, Patent Document 1 discloses another example of a semiconductor memory device in which a memory cell is constituted by only one transistor.
Patent Document 1: Japanese Patent Application Laid-Open No. 2002-260381.
However, according to the semiconductor memory device disclosed in Patent Document 1, a polysilicon pillar of a special structure needs to be formed, thereby making a process complicated and inviting an increase of a cost.
In the semiconductor memory device disclosed in Patent Document 1, by applying a high voltage between a source and a drain, impact ionization is caused in the vicinity of the drain, and holes generated thereby are accumulated in a body. Thus, writing of data “1” (in a state of low threshold voltage) is carried out. Moreover, by discharging holes from the body by applying a negative voltage to the source, writing of data “0” (in a state of high threshold voltage) is carried out. However, there is a limit in generating holes by impact ionization, thereby involving a problem that a difference of a threshold voltage can not be increased between the state of data “1” and the state of data “0”. Further, significantly various kind of power supply voltages are required for controlling reading and writing, and in addition, a driver for supplying voltages of 3 values are required for controlling a word line and a bit line, thereby also involving the problem that control of the reading and writing and generation of required voltage are complicated. Further, when the memory cell is constituted by only one memory transistor, in some cases, a potential of the body is maintained in a low state when power is input. In such a state, current does not flow by impact ionization, thus involving a problem that writing of data “1” can not be performed. In order to prevent such a situation, there is a problem that an extra procedure is required such that all memory cells are once initialized, thereby requiring higher power supply voltage than normal operation for initialization.